CV

Education

• B.S. in Electronics and Telecommunicaton, VNU University of Engineering and Technology, Vietnam, 2010
• M.S. in Network and Telecommunication, Paris-Sud XI University, France, 2012
• Ph.D in Nanoelectronics and Nanotechnology, EEATS, Grenoble-Alpes University (UGA), France, 2019

Work experience

• 2021-present: Assistant Professor
  • VNU Information Technology Institute, Vietnam National University, Hanoi
  • Teaching Digital Design & Computer Achitecture courses
  • Research engineer on Machine Learning and Hardware Security for IoT and their hardware implementation
• 2019-2021: Assistant Professor
  • VNU University of Engineering and Technology, Vietnam National University, Hanoi
  • Teaching Digital Design & Computer Architecture courses
  • Principle Investigator on various projects such as ADEN4IOT and SCAI
• 2017-2019: Research engineer
  • VNU University of Engineering and Technology
  • Conducting research on Hardware Security and Security Hardware for IoT
  • Principle engineer on BCAM Project: in charge of data encryption module and security mechanisms
• 2015-2017: Research engineer
  • CEA-Leti, Grenoble, France
  • Proposing and implementing a solution to secure Ultra-Low-Power IoT application
• 2010-2015: Teaching Assistant & Research engineer
  • VNU University of Engineering and Technology, Vietnam National University, Hanoi
  • Conducting research on Video Coding and implementing hardware accelerator for Video Coding based on H264/AVC standard
• 2008-2009: Intership
  • Toshiba-Coltech Software Laboratory, VNU University of Engineering and Technology, Vietnam National University, Hanoi
  • Studying and implementing Zoomable User Interface (ZUI) for embedded systems

Skills

• Hardware modeling, simulation, implementation and verification
  • Simulators: VCS (Synopsys), ModelSim/QuestaSim (Mentor Graphics), NCSim (Cadence)
  • Digital Hardware Implementation Flow: Design Compiler/IC Compiler/StarRC/IC Validator (Synopsys), Innovus (Cadence)
  • Mixed-Signal tools: Custom Compiler/Custom Sim/Hspice (Synopsys)
  • Opensource design tools: Ngspice, Magic, Xschem, Openlane, Openroad
• Hardware Description language
  • Verilog/SystemVerilog
  • VHDL
  • Chisel
  • SystemC
• Software design & scripting
  • Python
  • TCL
  • Scala
• Embedded system programming
  • C
  • C++

Publications

Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder

Duy-Hieu Bui, Xuan-Tu Tran, "Multi-level Design Methodology using SystemC and VHDL for JPEG Encoder." In the proceedings of The 2011 International Conference on Integrated Circuits and Devices in Vietnam (IEICE ICDV 2011), 2011.

A Hardware Architecture for Intra Prediction in H.264/AVC Encoder

Duy-Hieu Bui, Van Tran, Van Nguyen, Duc Ngo, Xuan-Tu Tran, "A Hardware Architecture for Intra Prediction in H.264/AVC Encoder." In the proceedings of 2012 IEICE International Conference on Integrated Circuits and Devices in Vietnam (ICDV 2012), 2012.

High-Performance Adaption of ARM Processor into Network-on-Chip Architectures

Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran, "High-Performance Adaption of ARM Processor into Network-on-Chip Architectures." In the proceedings of The 26th IEEE International System-on-Chip Conference (SOCC), 2013.

System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder

Hai-Phong Phan, Kiem-Hung Nguyen, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran, "System-on-Chip Testbed for Validating the Hardware Design of H.264/AVC Encoder." In the proceedings of REV: the 2013 National Conference on Electronics and Communications, 2013.

An Overview of H.264 Hardware Encoder Architectures including Low-Power Features

Ngoc Nguyen, Duy Bui, Nam Dang, Edith Beigne, Suzanne Lesecq, Pascal Vivet, Xuan Tran, "An Overview of H.264 Hardware Encoder Architectures including Low-Power Features." REV Journal on Electronics and Communications, 2014.

Xây dựng hệ thống mô phỏng và kiểm chứng cho bộ mã hoá tín hiệu video video H.264/AVC

Duy-Hieu Bui, Nam-Khanh Dang, Ngoc-Mai Nguyen, Kiem-Hung Nguyen, Xuan-Tu Tran, "Xây dựng hệ thống mô phỏng và kiểm chứng cho bộ mã hoá tín hiệu video video H.264/AVC." In the proceedings of REV-ECIT: National Conference on Electronics, Communications and Information Technology, 2014.

A Low-Cost Implementation of Advance Encryption Standard

Tien-Luan Vu, Van-Quy Quach, Duy-Hieu Bui, Xuan-Tu Tran, "A Low-Cost Implementation of Advance Encryption Standard." In the proceedings of The 5th International Conference on Integrated Circuits, Design, and Verification (ICDV 2014), 2014.

H.264/AVC Hardware Encoders and Low-Power Features

Ngoc-Mai Nguyen, Edith Beigne, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran, "H.264/AVC Hardware Encoders and Low-Power Features." In the proceedings of 2014: the 12th of the biennial IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), 2014.

Reducing Temporal Redundancy in MJPEG using Zipfian Estimation Techniques

Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, "Reducing Temporal Redundancy in MJPEG using Zipfian Estimation Techniques." In the proceedings of 2014: the 12th of the biennial IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS 2014), 2014.

Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications

Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigne, Xuan-Tu Tran, "Ultra Low-Power and Low-Energy 32-bit Datapath AES Architecture for IoT Applications." In the proceedings of The 2016 IEEE International Conference on Integrated Circuit Design and Technology, 2016.

AES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applications

Duy Bui, Diego Puschini, Simone Bacles-Min, Edith Beigne, Xuan Tran, "AES datapath optimization strategies for low-power low-energy multi-security-level Internet-of-Thing applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017.

?AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures

Xuan Tran, Tung Nguyen, Hai Phan, Duy Bui, "?AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2017.

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems

Marc Belleville, Anca Molnos, Gilles Sicard, Jean Christmann, Dominique Morche, Duy Bui, Diego Puschini, Suzanne Lesecq, Edith Beigne, "Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems." Journal of Low Power Electronics, 2017.

Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing

Quang-Linh Nguyen, Dinh-Lam Tran, Duy-Hieu Bui, Duc-Tho Mai, Xuan-Tu Tran, "Efficient Binary Arithmetic Encoder for HEVCwith Multiple Bypass Bin Processing." In the proceedings of The 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 2017.

Accurate and Low Complex Cell Histogram Generation by Bypass the Gradient of Pixel Computation

Huy-Hung Ho, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, "Accurate and Low Complex Cell Histogram Generation by Bypass the Gradient of Pixel Computation." In the proceedings of The 4th NAFOSTED Conference on Information and Computer Science (NICS), 2017.

An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing

Duy-Anh Nguyen, Huy-Hung Ho, Duy-Hieu Bui, Xuan-Tu Tran, "An Efficient Hardware Implementation of Artificial Neural Network based on Stochastic Computing." In the proceedings of 2018 The 5th NAFOSTED Conference on Information and Computer Science (NICS), 2018.

A Variable Precision Approach for Deep Neural Networks

Xuan-Tuyen Tran, Duy-Anh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, "A Variable Precision Approach for Deep Neural Networks." In the proceedings of International Conference on Advanced Technologies for Communications (ATC) 2019, 2019.

An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks

Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran, "An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks." In the proceedings of 2019 32nd IEEE International System-on-Chip Conference (SOCC), 2019.

A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization

Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, "A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization." In the proceedings of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2019.

Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Error in Stationary Blocks

Xuan Tran, Ngoc Nguyen, Duy Bui, Kiem Nguyen, Minh Pham, Cong Pham, "Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Error in Stationary Blocks." EAI Transactions on Industrial Networks and Intelligent Systems, 2020.

Talks

Research and Development Activities on RISC-V and its Applications for IoTs

November 05, 2020

Talk at Virtual, Tokyo, Japan

Security Hardware and Hardware Security for Ultra-low-power IoT: New challenges & Opportunities

September 10, 2021

ITI-Seminar at VNU-ITI, Hanoi, Vietnam

Teaching

Computer Architecture

Digital Design

Service and leadership

• IEICE Vietnam Section Representative (2020-2021)
• IEEE Solid-State Circuit Society
• IEEE Circuit & System Society